TY - JOUR
T1 - Large-Signal Model of Graphene Field- Effect Transistors - Part II: Circuit Performance Benchmarking
AU - Pasadas, Francisco
AU - Jiménez, David
PY - 2016/7/1
Y1 - 2016/7/1
N2 - © 2016 IEEE. This paper presents a circuit performance benchmarking using the large-signal model of graphene FET reported in Part I of this two-part paper. To test the model, it has been implemented in a circuit simulator. In particular, we have simulated a high-frequency performance amplifier, together with other circuits that take the advantage of the ambipolarity of graphene, such as a frequency doubler, an RF subharmonic mixer, and a multiplier phase detector. A variety of simulations comprising dc, transient dynamics, Bode diagram, S parameters, and power spectrum have been compared with experimental data to assess the validity of the model.
AB - © 2016 IEEE. This paper presents a circuit performance benchmarking using the large-signal model of graphene FET reported in Part I of this two-part paper. To test the model, it has been implemented in a circuit simulator. In particular, we have simulated a high-frequency performance amplifier, together with other circuits that take the advantage of the ambipolarity of graphene, such as a frequency doubler, an RF subharmonic mixer, and a multiplier phase detector. A variety of simulations comprising dc, transient dynamics, Bode diagram, S parameters, and power spectrum have been compared with experimental data to assess the validity of the model.
KW - Ambipolar electronics
KW - FET
KW - Verilog-A
KW - circuit performance benchmarking
KW - compact model
KW - graphene
KW - intrinsic capacitance
U2 - 10.1109/TED.2016.2563464
DO - 10.1109/TED.2016.2563464
M3 - Article
SN - 0018-9383
VL - 63
SP - 2942
EP - 2947
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
M1 - 7471463
ER -