Integration of NEMS resonators in a 65 nm CMOS technology

J. L. Muñoz Gamarra, P. Alcaide, E. Marigó, J. Giner, A. Uranga, J. Esteve, N. Barniol

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29 Citas (Scopus)

Resumen

In this work we study the feasibility to obtain the smallest CMOS-NEMS resonator using a sub-100 nm CMOS technology. The NEMS resonators are defined in a top-down approach using the available layers of the 65 nm CMOS technology from ST Microelectronics. A combination of dry and wet etching is developed in order to release the NEMS in an in-house post-CMOS process. Two different NEMS resonators are designed: 60 nm × 100 nm polysilicon and 90 nm × 180 nm copper clamped-clamped beams. The designed polysilicon CC Beam with a length of 1.5 lm, resonates at 232 MHz and is capable to provide the same mass sensitivity than a bottom-up silicon nanowire. © 2013 Elsevier B.V. All rights reserved.
Idioma originalInglés
Páginas (desde-hasta)246-249
PublicaciónMicroelectronic Enginering
Volumen110
DOI
EstadoPublicada - 1 ene 2013

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