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Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models

P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nunez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodrizucz, M. Nafria, F. V. Fernandez*

*Autor correspondiente de este trabajo

Producción científica: Informe/libroLibro de ActasInvestigaciónrevisión exhaustiva

Resumen

Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.

Idioma originalInglés
EditorialInstitute of Electrical and Electronics Engineers Inc.
Número de páginas4
ISBN (versión impresa)9781538651520
DOI
EstadoPublicada - 13 ago 2018

Serie de la publicación

NombreSMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

Huella

Profundice en los temas de investigación de 'Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models'. En conjunto forman una huella única.

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