Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability

Victor M. Van Santen*, Javier Diaz-Fortuny, Hussam Amrouch, Javier Martin-Martinez, Rosana Rodriguez, Rafael Castro-Lopez, Elisenda Roca, Francisco V. Fernandez, Jorg Henkel, Montserrat Nafria

*Corresponding author for this work

Research output: Book/ReportProceedingResearchpeer-review

8 Citations (Scopus)


Recent MOSFET devices exhibit a strong variability in their Bias Temperature Instability (BTI) induced degradation (e.g., Vth-shift). For identical stress patterns, each device exhibits unique degradation behavior. As BTI variability increases with shrinking device geometries, modeling BTI variability becomes essential. The challenge of modeling BTI variability is the significant time required to characterize a representative set of devices to properly calibrate the BTI variability model. In addition, (SPICE) circuit simulations under BTI variability are extremely time consuming. Both challenges originate from unique uncorrelated BTI behavior in each device. Each device features a unique set of defects with a unique state (occupied/unoccupied) in each defect. In this work, we tackle the characterization challenge by processing the data acquired from our parallel measurement setup with lightweight and fast defect extraction. Our novel weighted time lag plot defect parameter extraction, removes uncorrelated voltage noise and categorizes correlated noise (i.e., Random Telegraph Noise (RTN)) and discrete voltage steps (i.e., BTI). After the measurement data is processed, capture time, emission time and induced degradation of each defect can be extracted. After defect parameters are extracted, we can fit a bi-variate log-normal defect distribution and calibrate our BTI model. To employ a BTI variability model in circuit simulation, it must be able to model thousands of MOSFETs. Circuits consist of thousands of devices, each with unique behavior, resulting in computationally intensive modeling. Our GPU-based BTI variability model employs massive parallelism (beyond 1000 processing cores) found in graphic cards to model thousands of MOSFETs in seconds. Therefore, our novel defect parameter extraction methodology allows lightweight, yet accurate characterization of our model, while our model itself enables circuit simulations in large circuits as it models 100,000 MOSFETs in just 119s.

Original languageEnglish
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)9781538654798
Publication statusPublished - 25 May 2018

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026


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