Verificación de circuitos utilizando simulación simbólica de Netlists Verilog a nivel de puerta

R. Capillas, L. Ribas, J. Carrabina

Research output: Chapter in Book › Chapter › Research

Original language	Spanish
Title of host publication	X Congreso de Diseño de Circuitos Integrados y Sistemas
Place of Publication	Saragossa (ES)
Pages	165-169
Number of pages	4
Edition	1
Publication status	Published - 1 Nov 1995

Cite this

@inbook{333b68e2911f4c09ae69e2fb96132f8f,

title = "Verificaci{\'o}n de circuitos utilizando simulaci{\'o}n simb{\'o}lica de Netlists Verilog a nivel de puerta",

author = "R. Capillas and L. Ribas and J. Carrabina",

year = "1995",

month = nov,

day = "1",

language = "Espa{\~n}ol",

isbn = "978-84-600-9269-8",

pages = "165--169",

booktitle = "X Congreso de Dise{\~n}o de Circuitos Integrados y Sistemas",

edition = "1",

}