Trapped charge and stress induced leakage current (SILC) in tunnel SiO<inf>2</inf> layers of de-processed MOS non-volatile memory devices observed at the nanoscale

M. Lanza, M. Porti, M. Nafría, X. Aymerich, G. Ghidini, A. Sebastiani

Research output: Contribution to journalArticleResearchpeer-review

7 Citations (Scopus)

Abstract

In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8 nm thick SiO2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures. Crown Copyright © 2009.
Original languageEnglish
Pages (from-to)1188-1191
JournalMicroelectronics Reliability
Volume49
DOIs
Publication statusPublished - 1 Sep 2009

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