The Role of the Fermi Level Pinning in Gate Tunable Graphene-Semiconductor Junctions

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Abstract

© 2016 IEEE. Graphene-based transistors relying on a conventional structure cannot switch properly because of the absence of an energy gap in graphene. To overcome this limitation, a barristor device was proposed, whose operation is based on the modulation of the graphene-semiconductor (GS) Schottky barrier by means of a top gate, and demonstrating an ON-OFF current ratio up to 105. Such a large number is likely due to the realization of an ultraclean interface with virtually no interface trapped charge. However, it is indeed technologically relevant to know the impact that the interface trapped charges might have on the barristor's electrical properties. We have developed a physics-based model of the gate tunable GS heterostructure where nonidealities, such as Fermi level pinning and a 'bias-dependent barrier lowering effect' have been considered. Using the model, we have made a comprehensive study of the barristor's expected digital performance.
Original languageEnglish
Article number7582491
Pages (from-to)4521-4526
JournalIEEE Transactions on Electron Devices
Volume63
Issue number11
DOIs
Publication statusPublished - 1 Nov 2016

Keywords

  • Barristor
  • Fermi level pinning (FLP)
  • graphene based devices
  • semiconductor device modeling
  • tunable Schottky barrier

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