Abstract
In order to achieve a good level of reliability we use a test strategy based on Layout Level Design For Testability (LLDFT) rules. These rules prevent the faults or reduce the appearance probability of them. We apply a practical set of LLDFT rules on the cells of the library designed on the Centre Nacional de Microelectrònica in order to obtain a highly testable cell library. © 1993.
Original language | English |
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Pages (from-to) | 245-248 |
Journal | Microprocessing and Microprogramming |
Volume | 39 |
Issue number | 2-5 |
DOIs | |
Publication status | Published - 1 Jan 1993 |