Testability enhancement using physical design rules in a CMOS cell library

F. C. Blom; J. Oliver; M. Rullán; C. Ferrer

doi:10.1016/0165-6074(93)90098-6

Testability enhancement using physical design rules in a CMOS cell library

F. C. Blom, J. Oliver, M. Rullán, C. Ferrer

Research output: Contribution to journal › Article › Research › peer-review

Abstract

In order to achieve a good level of reliability we use a test strategy based on Layout Level Design For Testability (LLDFT) rules. These rules prevent the faults or reduce the appearance probability of them. We apply a practical set of LLDFT rules on the cells of the library designed on the Centre Nacional de Microelectrònica in order to obtain a highly testable cell library. © 1993.

Original language	English
Pages (from-to)	245-248
Journal	Microprocessing and Microprogramming
Volume	39
Issue number	2-5
DOIs	https://doi.org/10.1016/0165-6074(93)90098-6
Publication status	Published - 1 Jan 1993

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title = "Testability enhancement using physical design rules in a CMOS cell library",

abstract = "In order to achieve a good level of reliability we use a test strategy based on Layout Level Design For Testability (LLDFT) rules. These rules prevent the faults or reduce the appearance probability of them. We apply a practical set of LLDFT rules on the cells of the library designed on the Centre Nacional de Microelectr{\`o}nica in order to obtain a highly testable cell library. {\textcopyright} 1993.",

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AB - In order to achieve a good level of reliability we use a test strategy based on Layout Level Design For Testability (LLDFT) rules. These rules prevent the faults or reduce the appearance probability of them. We apply a practical set of LLDFT rules on the cells of the library designed on the Centre Nacional de Microelectrònica in order to obtain a highly testable cell library. © 1993.

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Testability enhancement using physical design rules in a CMOS cell library

Abstract

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