Testability enhancement using physical design rules in a CMOS cell library

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    Abstract

    In order to achieve a good level of reliability we use a test strategy based on Layout Level Design For Testability (LLDFT) rules. These rules prevent the faults or reduce the appearance probability of them. We apply a practical set of LLDFT rules on the cells of the library designed on the Centre Nacional de Microelectrònica in order to obtain a highly testable cell library. © 1993.
    Original languageEnglish
    Pages (from-to)245-248
    JournalMicroprocessing and Microprogramming
    Volume39
    Issue number2-5
    DOIs
    Publication statusPublished - 1 Jan 1993

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