Testability enhancement of a basic set of CMOS cells

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    Abstract

    Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrònica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design. Copyright © 1994 John Wiley & Sons, Ltd.
    Original languageEnglish
    Pages (from-to)279-288
    JournalQuality and Reliability Engineering International
    Volume10
    Issue number4
    DOIs
    Publication statusPublished - 1 Jan 1994

    Keywords

    • Layout‐level design for testability
    • Realistic fault

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