Test structure assembly for bump bond yield measurement on high density flip chip technologies

M. Ullán, M. Lozano, M. Chmeissani, G. Blanchot, E. Cabruja, J. García, M. Maiorino, R. Martínez, G. Pellegrini, C. Puigdengoles

    Research output: Contribution to journalArticleResearchpeer-review


    Modern flip chip technologies for imaging applications have achieved a very high integration level together with the possibility of large area assemblies. These developments have resulted in an enormous increase in the total number of bump bonds per assembly. Consequently, yield tests become difficult, and an accurate measurement of it is often discarded. This problem is aggravated in medical applications, where the critical information can be limited to a few pixels, and therefore, yield should be very close to 100%. In these cases, a variation of a small percentage in bump bond yield can make the difference between an usable and a non-usable assembly. Therefore, quantitative and precise measurement of bump bond yield is needed to characterize the quality of any high density flip chip technology for these applications. In this paper, we present a newly developed test structure for electrical measurement of the bump bond yield of high density flip chip technologies, allowing both optimization and statistical control of the process. This test structure facilitates the identification of possible process deviations with precise quantitative yield measurements. It also allows to pin point any localized systematic failure in the bump bonding process. The test structure has been used to evaluate the yield of different flip chip technologies and has contributed to their fine optimization where necessary. © 2005 Elsevier Ltd. All rights reserved.
    Original languageEnglish
    Pages (from-to)1095-1100
    JournalMicroelectronics Reliability
    Issue number7
    Publication statusPublished - 1 Jul 2006


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