Test Pattern Generator for NMOS Integrated Circuits.

Carles Ferrer Ramis, Jean Pierre Deschamps, Joan Oliver Malagelada, Jordi Carrabina Bordoll, Elena Valderrama Valles

Research output: Contribution to journalArticleResearchpeer-review


The test pattern generator presented in this paper uses a switch-level circuit description. Enrichment transistor networks of NMOS logic functions are represented by non-oriented graphs. In relation with test generation we use D-Algorithm, for which we have developed an enumerative path-searching method on the graph, beginning with minimal path, that pass over the edge representing the faulty transistor.
Original languageEnglish
Pages (from-to)81-91
Issue number2
Publication statusPublished - 1 Dec 1987


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