Sub-1-V CMOS proportional-to-absolute temperature references

Francisco Serra-Graells; José Luis Huertas

doi:10.1109/JSSC.2002.806258

Sub-1-V CMOS proportional-to-absolute temperature references

Francisco Serra-Graells, José Luis Huertas

Research output: Contribution to journal › Article › Research › peer-review

83 Citations (Scopus)

Abstract

This paper presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (μA) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-μW integrated PTAT references are presented and exhaustively tested for 1.2- and 0.35-μm very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+ > 60 dB. Hence, the resulting PTAT circuits are suitable for very-low voltage system-on-a-chip applications in digital CMOS technologies.

Original language	English
Pages (from-to)	84-88
Journal	IEEE Journal of Solid-State Circuits
Volume	38
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2002.806258
Publication status	Published - 1 Jan 2003

Keywords

CMOS
Log
Low voltage
Proportional-to-absolute temperature (PTAT)
Sub-1 V

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10.1109/JSSC.2002.806258

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@article{7562fe4f774e46a1bad0b5bf04ce6655,

title = "Sub-1-V CMOS proportional-to-absolute temperature references",

abstract = "This paper presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (μA) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-μW integrated PTAT references are presented and exhaustively tested for 1.2- and 0.35-μm very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+ > 60 dB. Hence, the resulting PTAT circuits are suitable for very-low voltage system-on-a-chip applications in digital CMOS technologies.",

keywords = "CMOS, Log, Low voltage, Proportional-to-absolute temperature (PTAT), Sub-1 V",

author = "Francisco Serra-Graells and Huertas, {Jos{\'e} Luis}",

year = "2003",

month = jan,

day = "1",

doi = "10.1109/JSSC.2002.806258",

language = "English",

volume = "38",

pages = "84--88",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - Sub-1-V CMOS proportional-to-absolute temperature references

AU - Serra-Graells, Francisco

AU - Huertas, José Luis

PY - 2003/1/1

Y1 - 2003/1/1

N2 - This paper presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (μA) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-μW integrated PTAT references are presented and exhaustively tested for 1.2- and 0.35-μm very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+ > 60 dB. Hence, the resulting PTAT circuits are suitable for very-low voltage system-on-a-chip applications in digital CMOS technologies.

AB - This paper presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (μA) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-μW integrated PTAT references are presented and exhaustively tested for 1.2- and 0.35-μm very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+ > 60 dB. Hence, the resulting PTAT circuits are suitable for very-low voltage system-on-a-chip applications in digital CMOS technologies.

KW - CMOS

KW - Log

KW - Low voltage

KW - Proportional-to-absolute temperature (PTAT)

KW - Sub-1 V

U2 - 10.1109/JSSC.2002.806258

DO - 10.1109/JSSC.2002.806258

M3 - Article

VL - 38

SP - 84

EP - 88

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 1

ER -