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Abstract
This paper reports the use of the Quasi-static Memdiode Model (QMM) for simulating Complementary Resistive Switching (CRS) devices. CRS arises from the anti-serial connection of two memristors and it is used for generating low and high-resistance regions in the I-V characteristic with the aim of mitigating the sneak-path conduction problem in crossbar arrays. Here, the use of the QMM for CRS in the form of a six terminal subcircuit is explored. While two terminals of the subcircuit correspond to the conventional input and output pins of the CRS structure, the rest provide information about the voltage at the central node, the low-voltage conductance of each device, and the low-voltage conductance of the whole structure. Special attention is paid to the simulation of the so-called table with legs hysteresis loop (resistance at fixed bias vs. write voltage), which is often invoked in connection with devices that exhibit switching activity at the two interfaces of a single dielectric layer. Because of the internal potential drop distribution, the switching process takes place alternately at one side of the structure or the other giving rise to a pseudo-CRS behavior. The flexibility of the proposed approach is demonstrated through a series of fitting exercises that involve experimental data reported in the literature. The model script for the SPICE simulator is also provided.
Original language | English |
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Journal | Solid-State Electronics |
Volume | 194 |
DOIs | |
Publication status | Published - 2022 |
Keywords
- Resistive switching
- Complementary resistive switching
- Memristor
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Dive into the research topics of 'SPICE model for complementary resistive switching devices based on anti-serially connected quasi-static memdiodes'. Together they form a unique fingerprint.Projects
- 1 Finished
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Fabricación, caracterización, simulación, modelado y aplicaciones de dispositivos de conmutación resistiva
Miranda Castellano, E. A. (Principal Investigator), Morell Perez, A. (Principal Investigator 2), Boquet Pujadas, G. (Collaborator), Macias Toro, E. H. (Collaborator), Muñoz Gorriz, J. (Collaborator), Lopez Vicario, J. (Investigator), Serrano Garcia, J. (Investigator), Suñe Tarruella, J. F. (Investigator) & Salvador Aguilera, E. (Collaborator)
Spanish Ministry of Economy and Competitiveness (MINECO)
1/01/18 → 30/09/21
Project: Research Projects and Other Grants