Reliability simulation for analog ICs: Goals, solutions, and challenges

A. Toro-Frías, P. Martín-Lloret, J. Martin-Martinez, R. Castro-López, E. Roca, R. Rodriguez, M. Nafria, F. V. Fernández

Research output: Contribution to journalArticleResearchpeer-review

28 Citations (Scopus)


© 2016 Elsevier B.V. The need for new tools and simulation methodologies to evaluate the impact of all reliability effects in ICs is a critical challenge for the electronic industry. Issues due to process-related variations (also known as spatial variability) are well-known and off-the-shelf simulation methods are available. On the other hand, models and simulation methods for the aging-related problems, which are becoming more important with each technology node, are far less mature, specially for analog ICs. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) cause a time-dependent variability that occurs together with the spatial variability. A fundamental missing piece in the design flow is an efficient and accurate simulation methodology for IC reliability. To this goal, several challenges should be addressed properly: the essential nature of the stochastic behavior of aging (and thus resorting to stochastic models rather than deterministic ones), the correlation between spatial and aging-related variability, and relationship between biasing, stress and aging in analog ICs, among others. This paper discusses some of these challenges in detail.
Original languageEnglish
Pages (from-to)341-348
JournalIntegration, the VLSI Journal
Publication statusPublished - 1 Sept 2016


  • Aging
  • Analog ICs
  • BTI
  • Process variability
  • Reliability
  • Simulation methodology


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