TY - JOUR
T1 - Reliability simulation for analog ICs: Goals, solutions, and challenges
AU - Toro-Frías, A.
AU - Martín-Lloret, P.
AU - Martin-Martinez, J.
AU - Castro-López, R.
AU - Roca, E.
AU - Rodriguez, R.
AU - Nafria, M.
AU - Fernández, F. V.
PY - 2016/9/1
Y1 - 2016/9/1
N2 - © 2016 Elsevier B.V. The need for new tools and simulation methodologies to evaluate the impact of all reliability effects in ICs is a critical challenge for the electronic industry. Issues due to process-related variations (also known as spatial variability) are well-known and off-the-shelf simulation methods are available. On the other hand, models and simulation methods for the aging-related problems, which are becoming more important with each technology node, are far less mature, specially for analog ICs. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) cause a time-dependent variability that occurs together with the spatial variability. A fundamental missing piece in the design flow is an efficient and accurate simulation methodology for IC reliability. To this goal, several challenges should be addressed properly: the essential nature of the stochastic behavior of aging (and thus resorting to stochastic models rather than deterministic ones), the correlation between spatial and aging-related variability, and relationship between biasing, stress and aging in analog ICs, among others. This paper discusses some of these challenges in detail.
AB - © 2016 Elsevier B.V. The need for new tools and simulation methodologies to evaluate the impact of all reliability effects in ICs is a critical challenge for the electronic industry. Issues due to process-related variations (also known as spatial variability) are well-known and off-the-shelf simulation methods are available. On the other hand, models and simulation methods for the aging-related problems, which are becoming more important with each technology node, are far less mature, specially for analog ICs. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) cause a time-dependent variability that occurs together with the spatial variability. A fundamental missing piece in the design flow is an efficient and accurate simulation methodology for IC reliability. To this goal, several challenges should be addressed properly: the essential nature of the stochastic behavior of aging (and thus resorting to stochastic models rather than deterministic ones), the correlation between spatial and aging-related variability, and relationship between biasing, stress and aging in analog ICs, among others. This paper discusses some of these challenges in detail.
KW - Aging
KW - Analog ICs
KW - BTI
KW - Process variability
KW - Reliability
KW - Simulation methodology
U2 - 10.1016/j.vlsi.2016.05.002
DO - 10.1016/j.vlsi.2016.05.002
M3 - Article
VL - 55
SP - 341
EP - 348
JO - Integration, the VLSI Journal
JF - Integration, the VLSI Journal
SN - 0167-9260
ER -