© 2017 IEEE. Near-threshold computing (NTC) poses stringent constraints on designing reliable circuits, as degradations have a magnified impact at lower supply voltages (Vdd) compared with super-threshold supply voltages. While phenomena, such as bias temperature instability (BTI) scale down with Vdd, mitigate their magnified impact with reduced degradations and, thus, have little impact on NTC reliability. Process variation (PV) and random telegraph noise (RTN) do not scale with Vdd and, therefore, become key reliability challenges in NTC. On the other hand, in super-threshold computing (STC), PV and BTI are the dominant phenomena, as BTI induces considerable degradations at nominal Vdd and PV imposes large enough shifts to matter at any supply voltage. Therefore, to allow Vdd-scaling from super-to near-threshold, we need to consider all of BTI, RTN, and PV. Ergo, we present a unified RTN and BTI model that models their shared physical origin and is validated against experimental data across a wide voltage range. Our unified model and PV model capture the joint impact of RTN, BTI, and PV within a probabilistic reliability estimation for NTC and STC circuits. We employed our proposed model to analyze the reliability of SRAM cells showing how taking error correction codes into account is able to mitigate the deleterious effects of BTI, RTN, and PV by 36% compared with unprotected circuits.
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - 1 Jan 2018|
- reliability engineering
- safety margin
- semiconductor device reliability