Performance-Driven Swich-Level Logic Synthesis

J. Riera, J. Velasco, Ll Ribas, J. Carrabina

Research output: Chapter in Book › Chapter › Research

Original language	English
Title of host publication	Proceedings of the XII Conference on Design of Circuits and Integrated Systems
Editors	García Franquelo, L., Torralba Silgado, A., Aguirre Echanove, M.A.
Place of Publication	Sevilla (ES)
Pages	293-298
Number of pages	5
Edition	1
Publication status	Published - 1 Nov 1997

Cite this

@inbook{45722736e45d4e0190df2c7b8367760a,

title = "Performance-Driven Swich-Level Logic Synthesis",

author = "J. Riera and J. Velasco and Ll Ribas and J. Carrabina",

year = "1997",

month = nov,

day = "1",

language = "English",

isbn = "84-88783-28-0",

pages = "293--298",

editor = "{Garc{\'i}a Franquelo, L.} and {Torralba Silgado, A.} and {Aguirre Echanove, M.A.}",

booktitle = "Proceedings of the XII Conference on Design of Circuits and Integrated Systems",

edition = "1",

}

TY - CHAP

T1 - Performance-Driven Swich-Level Logic Synthesis

AU - Riera, J.

AU - Velasco, J.

AU - Ribas, Ll

AU - Carrabina, J.

PY - 1997/11/1

Y1 - 1997/11/1

M3 - Chapter

SN - 84-88783-28-0

SP - 293

EP - 298

BT - Proceedings of the XII Conference on Design of Circuits and Integrated Systems

A2 - García Franquelo, L., null

A2 - Torralba Silgado, A., null

A2 - Aguirre Echanove, M.A., null

CY - Sevilla (ES)

ER -