On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits: Desing, Automation and Test in Europe (Conference Procedings)

TY - BOOK

T1 - On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits

T2 - Desing, Automation and Test in Europe (Conference Procedings)

AU - Ribas Xirgo, Lluis

AU - Carrabina Bordoll, Jordi

PY - 1998/6

Y1 - 1998/6

M3 - Proceeding

BT - On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits

CY - Los Alamitos, CA (USA) (US)

ER -