'On-the-fly' measurements of CMOS inverters performance degradation under pulsed stress

A. Crespo-Yepes, R. Ramos, E. Barajas, X. Aragones, D. Mateo, J. Martin-Martinez, R. Rodriguez, M. Nafria

Research output: Contribution to journalArticleResearchpeer-review


In this work, an 'on-the-fly' type technique for the characterization and monitoring of the CMOS inverter degradation, simultaneously to the application of pulsed voltage stresses, is presented. This technique allows analyzing the CMOS inverter performance degradation through the inversion voltage shifts measured during the application of rapid pulses. The observed degradation of the inversion voltage is described by an analytical equation that considers only the shifts of two device parameters, threshold voltage and mobility, of both transistors of the CMOS inverter.

Original languageEnglish
Journal2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020
Publication statusPublished - 1 Sept 2020


  • circuit performance degradation
  • CMOS inverters
  • CMOS technology
  • device aging
  • measurement technique
  • simultaneous stress-characterization


Dive into the research topics of ''On-the-fly' measurements of CMOS inverters performance degradation under pulsed stress'. Together they form a unique fingerprint.

Cite this