'On-the-fly' measurements of CMOS inverters performance degradation under pulsed stress

A. Crespo-Yepes; R. Ramos; E. Barajas; X. Aragones; D. Mateo; J. Martin-Martinez; R. Rodriguez; M. Nafria

doi:10.1109/EUROSOI-ULIS49407.2020.9365566

'On-the-fly' measurements of CMOS inverters performance degradation under pulsed stress

A. Crespo-Yepes, R. Ramos, E. Barajas, X. Aragones, D. Mateo, J. Martin-Martinez, R. Rodriguez, M. Nafria

Department of Electronic Engineering

Research output: Contribution to journal › Article › Research › peer-review

Abstract

In this work, an 'on-the-fly' type technique for the characterization and monitoring of the CMOS inverter degradation, simultaneously to the application of pulsed voltage stresses, is presented. This technique allows analyzing the CMOS inverter performance degradation through the inversion voltage shifts measured during the application of rapid pulses. The observed degradation of the inversion voltage is described by an analytical equation that considers only the shifts of two device parameters, threshold voltage and mobility, of both transistors of the CMOS inverter.

Original language	English
Journal	2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020
DOIs	https://doi.org/10.1109/EUROSOI-ULIS49407.2020.9365566
Publication status	Published - 1 Sept 2020

Keywords

circuit performance degradation
CMOS inverters
CMOS technology
device aging
measurement technique
simultaneous stress-characterization

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10.1109/EUROSOI-ULIS49407.2020.9365566

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Crespo-Yepes, A., Ramos, R., Barajas, E., Aragones, X., Mateo, D., Martin-Martinez, J., Rodriguez, R., & Nafria, M. (2020). 'On-the-fly' measurements of CMOS inverters performance degradation under pulsed stress. 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020. https://doi.org/10.1109/EUROSOI-ULIS49407.2020.9365566

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abstract = "In this work, an 'on-the-fly' type technique for the characterization and monitoring of the CMOS inverter degradation, simultaneously to the application of pulsed voltage stresses, is presented. This technique allows analyzing the CMOS inverter performance degradation through the inversion voltage shifts measured during the application of rapid pulses. The observed degradation of the inversion voltage is described by an analytical equation that considers only the shifts of two device parameters, threshold voltage and mobility, of both transistors of the CMOS inverter. ",

keywords = "circuit performance degradation, CMOS inverters, CMOS technology, device aging, measurement technique, simultaneous stress-characterization",

author = "A. Crespo-Yepes and R. Ramos and E. Barajas and X. Aragones and D. Mateo and J. Martin-Martinez and R. Rodriguez and M. Nafria",

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Crespo-Yepes, A, Ramos, R, Barajas, E, Aragones, X, Mateo, D, Martin-Martinez, J, Rodriguez, R & Nafria, M 2020, ''On-the-fly' measurements of CMOS inverters performance degradation under pulsed stress', 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020. https://doi.org/10.1109/EUROSOI-ULIS49407.2020.9365566

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AU - Crespo-Yepes, A.

AU - Ramos, R.

AU - Barajas, E.

AU - Aragones, X.

AU - Mateo, D.

AU - Martin-Martinez, J.

AU - Rodriguez, R.

AU - Nafria, M.

PY - 2020/9/1

Y1 - 2020/9/1

N2 - In this work, an 'on-the-fly' type technique for the characterization and monitoring of the CMOS inverter degradation, simultaneously to the application of pulsed voltage stresses, is presented. This technique allows analyzing the CMOS inverter performance degradation through the inversion voltage shifts measured during the application of rapid pulses. The observed degradation of the inversion voltage is described by an analytical equation that considers only the shifts of two device parameters, threshold voltage and mobility, of both transistors of the CMOS inverter.

AB - In this work, an 'on-the-fly' type technique for the characterization and monitoring of the CMOS inverter degradation, simultaneously to the application of pulsed voltage stresses, is presented. This technique allows analyzing the CMOS inverter performance degradation through the inversion voltage shifts measured during the application of rapid pulses. The observed degradation of the inversion voltage is described by an analytical equation that considers only the shifts of two device parameters, threshold voltage and mobility, of both transistors of the CMOS inverter.

KW - circuit performance degradation

KW - CMOS inverters

KW - CMOS technology

KW - device aging

KW - measurement technique

KW - simultaneous stress-characterization

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JO - 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020

JF - 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020

ER -

'On-the-fly' measurements of CMOS inverters performance degradation under pulsed stress

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Keywords

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