Morphological algorithms for visual analysis of integrated circuits

Jordi Vitrià, Xavier Binefa, Juan José Villanueva

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    Advances in integrated circuits technology lead to a continuous reduction in the size of individual features and to an increase in the size of chips and wafers. Every day it becomes more difficult to carry out tests and controls of quality and it is necessary to devise new techniques for accurate analysis of features, chips, and wafers. One of these procedures, visual inspection, can be achieved automatically by using image analysis techniques, with a high degree of automation and a low labor cost. We present a method for segmenting and classifying integrated circuit images based on one of these techniques: mathematical morphology. © 1992.
    Original languageEnglish
    Pages (from-to)194-202
    JournalJournal of Visual Communication and Image Representation
    Issue number2
    Publication statusPublished - 1 Jan 1992


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