TY - JOUR
T1 - Modeling of the degradation of CMOS inverters under pulsed stress conditions from ‘on-the-fly’ measurements
AU - Crespo-Yepes, A.
AU - Ramos, R.
AU - Barajas, E.
AU - Aragones, X.
AU - Mateo, D.
AU - Martin-Martinez, J.
AU - Rodriguez, R.
AU - Nafria, M.
N1 - Publisher Copyright:
© 2021 Elsevier Ltd
PY - 2021/10/1
Y1 - 2021/10/1
N2 - In this work, an 'on-the-fly' measurement technique for the monitoring of CMOS inverters performance degradation is presented. This technique allows the characterization of the circuit degradation simultaneously with the applications of the stress. In our experiments, the inversion voltage (VINV) shifts measured during the application of pulsed voltage stresses at the input. It is demonstrated that the shifts can be described by a power law that accounts for the stress time and voltage dependences. Moreover, the circuit degradation has been correlated to the NMOS and PMOS degradations. The results show that the degradation of the CMOS inverter can be evaluated from an analytical equation that considers only the shifts of two parameters (threshold voltage VTH, and mobility mu) of the two transistors in the inverter.
AB - In this work, an 'on-the-fly' measurement technique for the monitoring of CMOS inverters performance degradation is presented. This technique allows the characterization of the circuit degradation simultaneously with the applications of the stress. In our experiments, the inversion voltage (VINV) shifts measured during the application of pulsed voltage stresses at the input. It is demonstrated that the shifts can be described by a power law that accounts for the stress time and voltage dependences. Moreover, the circuit degradation has been correlated to the NMOS and PMOS degradations. The results show that the degradation of the CMOS inverter can be evaluated from an analytical equation that considers only the shifts of two parameters (threshold voltage VTH, and mobility mu) of the two transistors in the inverter.
KW - 'On-the-fly' stress characterization
KW - Analytical modelling
KW - CMOS inverters
KW - CMOS technology
KW - Circuit performance degradation
KW - Measurement technique
KW - Transistor aging
KW - ‘On-the-fly’ stress characterization
UR - http://www.scopus.com/inward/record.url?scp=85108302307&partnerID=8YFLogxK
UR - https://www.mendeley.com/catalogue/31584381-fdae-3962-b79f-1b335b5ddd89/
M3 - Article
AN - SCOPUS:85108302307
VL - 184
JO - Solid-State Electronics
JF - Solid-State Electronics
SN - 0038-1101
M1 - 108094
ER -