Modeling of the degradation of CMOS inverters under pulsed stress conditions from ‘on-the-fly’ measurements

A. Crespo-Yepes*, R. Ramos, E. Barajas, X. Aragones, D. Mateo, J. Martin-Martinez, R. Rodriguez, M. Nafria

*Corresponding author for this work

Research output: Contribution to journalArticleResearchpeer-review

Abstract

In this work, an 'on-the-fly' measurement technique for the monitoring of CMOS inverters performance degradation is presented. This technique allows the characterization of the circuit degradation simultaneously with the applications of the stress. In our experiments, the inversion voltage (VINV) shifts measured during the application of pulsed voltage stresses at the input. It is demonstrated that the shifts can be described by a power law that accounts for the stress time and voltage dependences. Moreover, the circuit degradation has been correlated to the NMOS and PMOS degradations. The results show that the degradation of the CMOS inverter can be evaluated from an analytical equation that considers only the shifts of two parameters (threshold voltage VTH, and mobility mu) of the two transistors in the inverter.

Original languageEnglish
Article number108094
Number of pages7
JournalSOLID-STATE ELECTRONICS
Volume184
DOIs
Publication statusPublished - 1 Oct 2021

Keywords

  • Analytical modelling
  • Circuit performance degradation
  • CMOS inverters
  • CMOS technology
  • Measurement technique
  • Transistor aging
  • ‘On-the-fly’ stress characterization
  • 'On-the-fly' stress characterization

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