Layout-Level Design for Testability Strategy applied to a CMOS Cell Library

Research output: Chapter in Book › Chapter › Research

Original language	English
Title of host publication	Proceedings del International Workshop on Defect and Fault Tolerance in VLSI Systems
Place of Publication	Los Alamitos (US)
Pages	199-206
Number of pages	7
Edition	1
Publication status	Published - 1 Jan 1993

Cite this

@inbook{92a2f0b378c940fca916596b5e3541b8,

title = "Layout-Level Design for Testability Strategy applied to a CMOS Cell Library",

author = "F.C. Blom and J. Oliver and M. Rullan and C. Ferrer",

year = "1993",

month = jan,

day = "1",

language = "English",

isbn = "0-8186-3502-9",

pages = "199--206",

booktitle = "Proceedings del International Workshop on Defect and Fault Tolerance in VLSI Systems",

edition = "1",

}