Layout-Level Design for Testability Strategy applied to a CMOS Cell Library

    Research output: Chapter in BookChapterResearch

    Original languageEnglish
    Title of host publicationProceedings del International Workshop on Defect and Fault Tolerance in VLSI Systems
    Place of PublicationLos Alamitos (US)
    Pages199-206
    Number of pages7
    Edition1
    Publication statusPublished - 1 Jan 1993

    Cite this

    Blom, F. C., Oliver, J., Rullan, M., & Ferrer, C. (1993). Layout-Level Design for Testability Strategy applied to a CMOS Cell Library. In Proceedings del International Workshop on Defect and Fault Tolerance in VLSI Systems (1 ed., pp. 199-206).