Layout Level Design for Testability Rules for a CMOS Cell Library

M. Rullán, F.C. Blom, J. Oliver, C. Ferrer

    Research output: Chapter in BookChapterResearch

    Original languageEnglish
    Title of host publicationProceedings of the EURO-DAC
    Editors ISBN: 0-8186-4350-1
    Place of Publication(US)
    Pages214-218
    Number of pages4
    Edition1
    Publication statusPublished - 1 Jan 1993

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