Layout Level Design for Testability Rules for a CMOS Cell Library

M. Rullán, F.C. Blom, J. Oliver, C. Ferrer

    Research output: Chapter in BookChapterResearch

    Original languageEnglish
    Title of host publicationProceedings of the EURO-DAC
    Editors ISBN: 0-8186-4350-1
    Place of Publication(US)
    Number of pages4
    Publication statusPublished - 1 Jan 1993

    Cite this