Large-Signal Model of Graphene Field-Effect Transistors - Part I: Compact Modeling of GFET Intrinsic Capacitances

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Abstract

© 2016 IEEE. We present a circuit-compatible compact model of the intrinsic capacitances of GFETs. Together with a compact drain current model, a large-signal model is developed combining both models as a tool for simulating the electrical behavior of graphene-based integrated circuits, dealing with the dc, transient behavior, and frequency response of the circuit. The drain current model is based on a drift-diffusion mechanism for the carrier transport coupled with an appropriate field-effect approach. The intrinsic capacitance model consists of a 16-capacitance matrix including self-capacitances and transcapacitances of a four-terminal GFET. To guarantee charge conservation, a Ward-Dutton linear charge partition scheme has been used. The large-signal model has been implemented in Verilog-A, being compatible with conventional circuit simulators and serving as a starting point toward the complete GFET device model that could incorporate additional nonidealities.
Original languageEnglish
Article number7480420
Pages (from-to)2936-2941
JournalIEEE Transactions on Electron Devices
Volume63
DOIs
Publication statusPublished - 1 Jul 2016

Keywords

  • Compact model
  • FET
  • Verilog-A
  • drift-diffusion (DD)
  • graphene
  • intrinsic capacitance

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