Hardware Counters’ Space Reduction for Code Region Characterization

Jordi Alcaraz*, Anna Sikora, Eduardo César

*Corresponding author for this work

Research output: Chapter in BookChapterResearchpeer-review

Abstract

This work proposes that parallel code regions in an OpenMP application can be characterized using a signature composed by the values of a set of hardware performance counters. Our proposal is aimed towards dynamic tuning and, consequently, the metrics must be collected at execution time, which limits the number of metrics that can be measured. Therefore, our main contribution is the definition of a methodology to determine a reduced set of hardware performance counters that can be measured at application’s execution time and that still contains enough information to characterize a parallel region. The proposed methodology is based on principal component analysis and linear correlation analysis. Preliminary results show that it can be used to successfully reduce the number of hardware counters needed to characterize a parallel region, and that this set of counters can be measured at run time with high accuracy and low overhead using counter multiplexing.

Original languageAmerican English
Title of host publicationEuro-Par 2019
Subtitle of host publicationParallel Processing - 25th International Conference on Parallel and Distributed Computing, Proceedings
EditorsRamin Yahyapour
Pages74-86
Number of pages13
DOIs
Publication statusPublished - 2019

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume11725 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Keywords

  • Hardware counters
  • Parallel/distributed applications
  • Performance analysis

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