Gate dielectric degradation in CMOS inverters

J. Martín-Martínez, S. Gerardin, R. Rodríguez, M. Nafría, X. Aymerich, A. Paccagnella, G. Ghidini

Research output: Contribution to journalArticleResearchpeer-review

Abstract

To study the gate oxide degradation under stress conditions closer to the actual operation of devices in circuits, in this work, CMOS inverters have been stressed using DC and pulsed signals at the input. Uniform and non-uniform Fowler-Nordheim and Channel Hot Carrier stresses have been identified as those governing the oxide degradation, depending on the input signal, and modifying the electrical response of the device. In particular, a decrease of the saturation current is observed, which depends on the transistor type (NMOS or PMOS), input signal, and stress time. The results show larger degradations in the NMOS when the input frequency is increased, which has been attributed to the Channel Hot Carriers contribution during the output state transitions in the inverter. Also the impact of the different stresses on the circuit output is analyzed and related to the degradation of the devices. A shift in the inverter voltage transfer characteristic has been observed, whose direction depends on the degradation that the transistors have suffered, being more important at elevated frequencies. © 2009 Elsevier B.V. All rights reserved.
Original languageEnglish
Pages (from-to)2123-2126
JournalMicroelectronic Engineering
Volume86
DOIs
Publication statusPublished - 1 Oct 2009

Keywords

  • CMOS circuits
  • Oxide reliability

Fingerprint Dive into the research topics of 'Gate dielectric degradation in CMOS inverters'. Together they form a unique fingerprint.

Cite this