Fabrication of CMOS retrograde wells by doping compensation with ion implantation

J. Montserrat; J. Bausells; E. Lora-Tamayo; F. Serra-Mestres

doi:10.1016/0042-207X(89)90017-1

Fabrication of CMOS retrograde wells by doping compensation with ion implantation

J. Montserrat, J. Bausells, E. Lora-Tamayo, F. Serra-Mestres

Department of Physics

Research output: Contribution to journal › Article › Research › peer-review

2 Citations (Scopus)

Abstract

A process for a retrograde well obtained by partial compensation of doping in the surface region is described. This structure is useful to reduce the latch-up susceptibility in CMOS technology. The process has been designed using the SUPREM program. Sample characterization has been carried out by the spreading resistance technique and by the four-point probe method. Good agreement has been obtained between simulated and experimental values. © 1989.

Original language	English
Pages (from-to)	687-690
Journal	Vacuum
Volume	39
Issue number	7-8
DOIs	https://doi.org/10.1016/0042-207X(89)90017-1
Publication status	Published - 1 Jan 1989

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10.1016/0042-207X(89)90017-1

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title = "Fabrication of CMOS retrograde wells by doping compensation with ion implantation",

abstract = "A process for a retrograde well obtained by partial compensation of doping in the surface region is described. This structure is useful to reduce the latch-up susceptibility in CMOS technology. The process has been designed using the SUPREM program. Sample characterization has been carried out by the spreading resistance technique and by the four-point probe method. Good agreement has been obtained between simulated and experimental values. {\textcopyright} 1989.",

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T1 - Fabrication of CMOS retrograde wells by doping compensation with ion implantation

AU - Montserrat, J.

AU - Bausells, J.

AU - Lora-Tamayo, E.

AU - Serra-Mestres, F.

PY - 1989/1/1

Y1 - 1989/1/1

N2 - A process for a retrograde well obtained by partial compensation of doping in the surface region is described. This structure is useful to reduce the latch-up susceptibility in CMOS technology. The process has been designed using the SUPREM program. Sample characterization has been carried out by the spreading resistance technique and by the four-point probe method. Good agreement has been obtained between simulated and experimental values. © 1989.

AB - A process for a retrograde well obtained by partial compensation of doping in the surface region is described. This structure is useful to reduce the latch-up susceptibility in CMOS technology. The process has been designed using the SUPREM program. Sample characterization has been carried out by the spreading resistance technique and by the four-point probe method. Good agreement has been obtained between simulated and experimental values. © 1989.

U2 - 10.1016/0042-207X(89)90017-1

DO - 10.1016/0042-207X(89)90017-1

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SP - 687

EP - 690

JO - Vacuum

JF - Vacuum

SN - 0042-207X

IS - 7-8

ER -

Fabrication of CMOS retrograde wells by doping compensation with ion implantation

Abstract

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