Abstract
We propose an equivalent circuit model for the post-breakdown (BD) current-voltage (I - V) characteristics in HfO2/TaN/TiN gate stacks in n-MOSFETs. The model consists of two opposite-biased diodes with series resistances and a shunt leakage path. The circuit admits analytical solution using the Lambert W-function and is tested for both negative and positive gate biases in the voltage range of -1.5 to +1.5 V. We also show the versatility of the proposed approach to deal with the post-BD I - V when source and drain contacts are grounded or floating and analyze the obtained results in terms of the charge available for conduction. © 2008 IEEE.
Original language | English |
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Pages (from-to) | 1353-1355 |
Journal | IEEE Electron Device Letters |
Volume | 29 |
DOIs | |
Publication status | Published - 8 Dec 2008 |
Keywords
- Dielectric breakdown (BD)
- High-κ
- MOSFET