A conductive atomic force microscope (CAFM) has been used to study, at the nanometre scale, the dependence of the electrical behaviour on the post-deposition annealing temperature (TA) and the dielectric reliability of ultrathin high-dielectric-constant/SiO2 MOS gate stacks. It has been observed that for high enough TA the conduction becomes more inhomogeneous, leading to the formation of leaky spots that could be a problem for the integration of these layers in a standard CMOS microelectronic process. The CAFM has also revealed that the values of some parameters related to the dielectric reliability, such as the area of the breakdown spot (i.e. a region that has lost its insulating properties owing to electrical stress), are of the same order for SiO2 layers and high-dielectric-constant/SiO2 stacks. Moreover, different conduction regimes, which cannot be detected by standard electrical characterization techniques, have been observed. © 2005 IOP Publishing Ltd.