Efficiently Mapping VLSI Circuits with Simple Cells

Jody Maick Matos, Jordi Carrabina, Andre Reis

Research output: Contribution to journalArticleResearch

1 Citation (Scopus)

Abstract

© 1982-2012 IEEE. This paper presents two main contributions toward efficient very large scale integration circuits mapped with simple cells: 1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and 2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. An effective pattern-based algorithm to identify XORs/XNORs on and-inverter graphs is also presented. We show that efficient implementations in terms of inverter count, transistor count, area, power, and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while: 1) optimizing the number of added inverters and 2) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation, and delay up to 48%, 4%, 8%, 14%, and 16%, respectively.
Original languageEnglish
Article number8323227
Pages (from-to)692-704
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume38
DOIs
Publication statusPublished - 1 Apr 2019

Keywords

  • Logic synthesis
  • simple cells
  • standard cell library
  • technology mapping

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