Skip to main navigation Skip to search Skip to main content

Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models

P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nunez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodrizucz, M. Nafria, F. V. Fernandez*

*Corresponding author for this work

Research output: Book/ReportProceedingResearchpeer-review

Abstract

Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.

Original languageEnglish
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)9781538651520
DOIs
Publication statusPublished - 13 Aug 2018

Publication series

NameSMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

Fingerprint

Dive into the research topics of 'Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models'. Together they form a unique fingerprint.

Cite this