To allow real performance-driven logic synthesis, area, power and delay trade-off should be considered from the very early stages of the synthesis process. Accurate models must be provided for area occupation, delay, and power dissipation. Moreover, the model parameters should be available during all stages of logic synthesis. In this paper we present the models and derive cost functions to calculate their parameters. At the early stages of logic synthesis, generic cell library information and statistical data extracted from real integrated circuits (IC) are used to calculate the model parameters. As the synthesis process progress, technology dependent information becomes available and the model parameters are gradually refined. © 1997 Elsevier Science B.V. All rights reserved.
|Journal||Journal of Systems Architecture|
|Publication status||Published - 1 Jan 1997|
- Performance-driven combinatinal logic synthesis