Deposited thin SiO2 for gate oxide on n-type and p-type GaN

M. Placidi, A. Constant, A. Fontser̀, E. Pausas, I. Cortes, Y. Cordier, N. Mestres, R. Ṕrez, M. Zabala, J. Millán, P. Godignon, A. Ṕérez-Tomás

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    Here, we report on a comparison of two different methods to achieve thin SiO2 deposited layers for gate oxide on n- and p-type GaN by using plasma-enhanced chemical vapor deposition with silane (SiH4) and tetraethyl orthosilicate (Si [OC2H5]4) precursors. An annealing was performed at 800°C for 2 min in N2 ambient as an attempt to improve electrical characteristics. Before and after annealing, capacitors were electrical/physically analyzed by capacitance-voltage (C-V), conductance-voltage, current-voltage, optical microscope, scanning electron microscope, atomic force microscope, and secondary-ion mass spectrometry. Globally, the p-type samples presented higher interface state density and rougher surfaces, and in some C-V measurements, it is possible to observe inversion-like characteristics. The surface roughness also increases after annealing. The interfacial trap density for the different SiO2 /GaN interfaces has been determined. Silane samples exhibit lower Dit than TEOS samples. For n-type, annealed SiO2 from silane has been found as the sample with the lowest Dit. The annealing on the SiO2 from silane samples is not so efficient for the p-type with the Dit actually increasing. A discussion on the different diffusion mechanisms in correlation with the electrical results is performed in the last section of this paper. © 2010 The Electrochemical Society.
    Original languageEnglish
    JournalJournal of the Electrochemical Society
    Issue number11
    Publication statusPublished - 1 Jan 2010


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