Comparison of SiO<inf>2</inf> and HfO<inf>2</inf>/SiO<inf>2</inf> gate stacks electrical behaviour at a nanometre scale with CAFM

X. Blasco; M. Nafría; X. Aymerich; W. Vandervorst

doi:https://doi.org/10.1049/el:20050805

Comparison of SiO<inf>2</inf> and HfO<inf>2</inf>/SiO<inf>2</inf> gate stacks electrical behaviour at a nanometre scale with CAFM

X. Blasco, M. Nafría, X. Aymerich, W. Vandervorst

Department of Electronic Engineering

Research output: Contribution to journal › Article › Research › peer-review

6 Citations (Scopus)

Abstract

The electrical behaviour of a SiO2 gate layer and a HfO 2/SiO2 gate stack are studied at the nanometre scale by means of CAFM. The leaky spot (LS) and breakdown (BD) spot sizes, the post BD current-voltage (I-V) characteristics and the topography features have been compared. LS of ∼ 600-700 nm2 and BD sizes of 1000-3000 nm 2 are measured for the SiO2 layer and the HfO 2/SiO2 stack. Post BD I-V characteristics reveal that, for SiO2, I-V curves are well grouped and CAFM compliance is always reached for Vgate < 0.5 V. For the HfO2/SiO2 stack, I-V curves show very much dispersion, and the Vgate needed to reach the compliance is larger. Therefore, the high-k layer reduces the severity of the BD event. Even so, a few times the HfO2/SiO 2 stack BD spots exhibit I-V characteristics as conductive as SiO2 BD spots. © IEE 2005.

Original language	English
Pages (from-to)	719-721
Journal	Electronics Letters
Volume	41
DOIs	https://doi.org/10.1049/el:20050805
Publication status	Published - 9 Jun 2005

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title = "Comparison of SiO2 and HfO2/SiO2 gate stacks electrical behaviour at a nanometre scale with CAFM",

abstract = "The electrical behaviour of a SiO2 gate layer and a HfO 2/SiO2 gate stack are studied at the nanometre scale by means of CAFM. The leaky spot (LS) and breakdown (BD) spot sizes, the post BD current-voltage (I-V) characteristics and the topography features have been compared. LS of ∼ 600-700 nm2 and BD sizes of 1000-3000 nm 2 are measured for the SiO2 layer and the HfO 2/SiO2 stack. Post BD I-V characteristics reveal that, for SiO2, I-V curves are well grouped and CAFM compliance is always reached for Vgate < 0.5 V. For the HfO2/SiO2 stack, I-V curves show very much dispersion, and the Vgate needed to reach the compliance is larger. Therefore, the high-k layer reduces the severity of the BD event. Even so, a few times the HfO2/SiO 2 stack BD spots exhibit I-V characteristics as conductive as SiO2 BD spots. {\textcopyright} IEE 2005.",

author = "X. Blasco and M. Nafr{\'i}a and X. Aymerich and W. Vandervorst",

year = "2005",

month = jun,

day = "9",

doi = "https://doi.org/10.1049/el:20050805",

language = "English",

volume = "41",

pages = "719--721",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

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TY - JOUR

T1 - Comparison of SiO2 and HfO2/SiO2 gate stacks electrical behaviour at a nanometre scale with CAFM

AU - Blasco, X.

AU - Nafría, M.

AU - Aymerich, X.

AU - Vandervorst, W.

PY - 2005/6/9

Y1 - 2005/6/9

N2 - The electrical behaviour of a SiO2 gate layer and a HfO 2/SiO2 gate stack are studied at the nanometre scale by means of CAFM. The leaky spot (LS) and breakdown (BD) spot sizes, the post BD current-voltage (I-V) characteristics and the topography features have been compared. LS of ∼ 600-700 nm2 and BD sizes of 1000-3000 nm 2 are measured for the SiO2 layer and the HfO 2/SiO2 stack. Post BD I-V characteristics reveal that, for SiO2, I-V curves are well grouped and CAFM compliance is always reached for Vgate < 0.5 V. For the HfO2/SiO2 stack, I-V curves show very much dispersion, and the Vgate needed to reach the compliance is larger. Therefore, the high-k layer reduces the severity of the BD event. Even so, a few times the HfO2/SiO 2 stack BD spots exhibit I-V characteristics as conductive as SiO2 BD spots. © IEE 2005.

AB - The electrical behaviour of a SiO2 gate layer and a HfO 2/SiO2 gate stack are studied at the nanometre scale by means of CAFM. The leaky spot (LS) and breakdown (BD) spot sizes, the post BD current-voltage (I-V) characteristics and the topography features have been compared. LS of ∼ 600-700 nm2 and BD sizes of 1000-3000 nm 2 are measured for the SiO2 layer and the HfO 2/SiO2 stack. Post BD I-V characteristics reveal that, for SiO2, I-V curves are well grouped and CAFM compliance is always reached for Vgate < 0.5 V. For the HfO2/SiO2 stack, I-V curves show very much dispersion, and the Vgate needed to reach the compliance is larger. Therefore, the high-k layer reduces the severity of the BD event. Even so, a few times the HfO2/SiO 2 stack BD spots exhibit I-V characteristics as conductive as SiO2 BD spots. © IEE 2005.

U2 - https://doi.org/10.1049/el:20050805

DO - https://doi.org/10.1049/el:20050805

M3 - Article

VL - 41

SP - 719

EP - 721

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

ER -

Comparison of SiO<inf>2</inf> and HfO<inf>2</inf>/SiO<inf>2</inf> gate stacks electrical behaviour at a nanometre scale with CAFM

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