The electrical behaviour of a SiO2 gate layer and a HfO 2/SiO2 gate stack are studied at the nanometre scale by means of CAFM. The leaky spot (LS) and breakdown (BD) spot sizes, the post BD current-voltage (I-V) characteristics and the topography features have been compared. LS of ∼ 600-700 nm2 and BD sizes of 1000-3000 nm 2 are measured for the SiO2 layer and the HfO 2/SiO2 stack. Post BD I-V characteristics reveal that, for SiO2, I-V curves are well grouped and CAFM compliance is always reached for Vgate < 0.5 V. For the HfO2/SiO2 stack, I-V curves show very much dispersion, and the Vgate needed to reach the compliance is larger. Therefore, the high-k layer reduces the severity of the BD event. Even so, a few times the HfO2/SiO 2 stack BD spots exhibit I-V characteristics as conductive as SiO2 BD spots. © IEE 2005.