Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications

Oana Moldovan; Antonio Cerdeira; David Jiménez; Jean Pierre Raskin; Valeria Kilchytska; Denis Flandre; Nadine Collaert; Benjamin Iñiguez

doi:https://doi.org/10.1016/j.sse.2007.02.039

Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications

Oana Moldovan, Antonio Cerdeira, David Jiménez, Jean Pierre Raskin, Valeria Kilchytska, Denis Flandre, Nadine Collaert, Benjamin Iñiguez

Department of Electronic Engineering

Research output: Contribution to journal › Article › Research › peer-review

63 Citations (Scopus)

Abstract

An analytical and continuous model for a highly-doped double-gate SOI MOSFET, in which the channel current is expressed as an explicit function of the applied voltages, is presented targeting the electrical simulation of baseband analog circuits. A unified charge control model is for the first time derived for doped double-gate transistors. It is valid from below to well above threshold, showing a smooth transition between the regimes. Small-signal parameters can be obtained from the model. The calculated current and capacitance characteristics show a good agreement with 2D numerical device simulations, in all regimes, and also a very good match to FinFET experimental data, in the case of the drain current. © 2007 Elsevier Ltd. All rights reserved.

Original language	English
Pages (from-to)	655-661
Journal	Solid-State Electronics
Volume	51
DOIs	https://doi.org/10.1016/j.sse.2007.02.039
Publication status	Published - 1 May 2007

Keywords

Compact device modelling
Double-gate MOSFET
Intrinsic capacitances
Parasitic capacitances

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https://doi.org/10.1016/j.sse.2007.02.039

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title = "Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications",

abstract = "An analytical and continuous model for a highly-doped double-gate SOI MOSFET, in which the channel current is expressed as an explicit function of the applied voltages, is presented targeting the electrical simulation of baseband analog circuits. A unified charge control model is for the first time derived for doped double-gate transistors. It is valid from below to well above threshold, showing a smooth transition between the regimes. Small-signal parameters can be obtained from the model. The calculated current and capacitance characteristics show a good agreement with 2D numerical device simulations, in all regimes, and also a very good match to FinFET experimental data, in the case of the drain current. {\textcopyright} 2007 Elsevier Ltd. All rights reserved.",

keywords = "Compact device modelling, Double-gate MOSFET, Intrinsic capacitances, Parasitic capacitances",

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T1 - Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications

AU - Moldovan, Oana

AU - Cerdeira, Antonio

AU - Jiménez, David

AU - Raskin, Jean Pierre

AU - Kilchytska, Valeria

AU - Flandre, Denis

AU - Collaert, Nadine

AU - Iñiguez, Benjamin

PY - 2007/5/1

Y1 - 2007/5/1

N2 - An analytical and continuous model for a highly-doped double-gate SOI MOSFET, in which the channel current is expressed as an explicit function of the applied voltages, is presented targeting the electrical simulation of baseband analog circuits. A unified charge control model is for the first time derived for doped double-gate transistors. It is valid from below to well above threshold, showing a smooth transition between the regimes. Small-signal parameters can be obtained from the model. The calculated current and capacitance characteristics show a good agreement with 2D numerical device simulations, in all regimes, and also a very good match to FinFET experimental data, in the case of the drain current. © 2007 Elsevier Ltd. All rights reserved.

AB - An analytical and continuous model for a highly-doped double-gate SOI MOSFET, in which the channel current is expressed as an explicit function of the applied voltages, is presented targeting the electrical simulation of baseband analog circuits. A unified charge control model is for the first time derived for doped double-gate transistors. It is valid from below to well above threshold, showing a smooth transition between the regimes. Small-signal parameters can be obtained from the model. The calculated current and capacitance characteristics show a good agreement with 2D numerical device simulations, in all regimes, and also a very good match to FinFET experimental data, in the case of the drain current. © 2007 Elsevier Ltd. All rights reserved.

KW - Compact device modelling

KW - Double-gate MOSFET

KW - Intrinsic capacitances

KW - Parasitic capacitances

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DO - https://doi.org/10.1016/j.sse.2007.02.039

M3 - Article

VL - 51

SP - 655

EP - 661

JO - Solid-State Electronics

JF - Solid-State Electronics

SN - 0038-1101

ER -

Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications

Abstract

Keywords

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