Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications

Oana Moldovan, Antonio Cerdeira, David Jiménez, Jean Pierre Raskin, Valeria Kilchytska, Denis Flandre, Nadine Collaert, Benjamin Iñiguez

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57 Citations (Scopus)

Abstract

An analytical and continuous model for a highly-doped double-gate SOI MOSFET, in which the channel current is expressed as an explicit function of the applied voltages, is presented targeting the electrical simulation of baseband analog circuits. A unified charge control model is for the first time derived for doped double-gate transistors. It is valid from below to well above threshold, showing a smooth transition between the regimes. Small-signal parameters can be obtained from the model. The calculated current and capacitance characteristics show a good agreement with 2D numerical device simulations, in all regimes, and also a very good match to FinFET experimental data, in the case of the drain current. © 2007 Elsevier Ltd. All rights reserved.
Original languageEnglish
Pages (from-to)655-661
JournalSolid-State Electronics
Volume51
DOIs
Publication statusPublished - 1 May 2007

Keywords

  • Compact device modelling
  • Double-gate MOSFET
  • Intrinsic capacitances
  • Parasitic capacitances

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    Moldovan, O., Cerdeira, A., Jiménez, D., Raskin, J. P., Kilchytska, V., Flandre, D., Collaert, N., & Iñiguez, B. (2007). Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications. Solid-State Electronics, 51, 655-661. https://doi.org/10.1016/j.sse.2007.02.039