Abstract
An analytical and continuous model for a highly-doped double-gate SOI MOSFET, in which the channel current is expressed as an explicit function of the applied voltages, is presented targeting the electrical simulation of baseband analog circuits. A unified charge control model is for the first time derived for doped double-gate transistors. It is valid from below to well above threshold, showing a smooth transition between the regimes. Small-signal parameters can be obtained from the model. The calculated current and capacitance characteristics show a good agreement with 2D numerical device simulations, in all regimes, and also a very good match to FinFET experimental data, in the case of the drain current. © 2007 Elsevier Ltd. All rights reserved.
Original language | English |
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Pages (from-to) | 655-661 |
Journal | Solid-State Electronics |
Volume | 51 |
DOIs | |
Publication status | Published - 1 May 2007 |
Keywords
- Compact device modelling
- Double-gate MOSFET
- Intrinsic capacitances
- Parasitic capacitances