Compact capacitance modeling of a 3-terminal FET at zero drain-source voltage

Benjamin Iñiguez, Oana Moldovan

Research output: Contribution to journalArticleResearchpeer-review

5 Citations (Scopus)

Abstract

The accuracy and continuity of the C-V characteristics of a transistor at Vds = 0 is one of the main benchmark tests a good compact model must pass. Singularities (in the form of 0/0 divisions) at Vds = 0 in compact capacitance models developed for several types of undoped 3-terminal devices, such as Double-Gate and Surrounding-Gate MOSFETs, have been corrected by means of techniques based on dealing individually with each of the targeted devices. Due to the lengthy calculations required for each of those particular cases, it will be useful to develop relationships between capacitances, with expressions easy to calculate, that can be applied to any type of undoped 3-terminal FET. We present compact modeling schemes valid for long-channel 3-terminal devices at Vds = 0 and we demonstrate suitable relationships between the different capacitances, deriving general analytic expressions for them in terms of the derivative of the drain charge sheet density with respect to the drain voltage; we also show how they can be calculated using the device charge control model. © 2010 Elsevier Ltd. All rights reserved.
Original languageEnglish
Pages (from-to)520-523
JournalSolid-State Electronics
Volume54
Issue number5
DOIs
Publication statusPublished - 1 May 2010

Keywords

  • Compact device modeling
  • Double-Gate MOSFETs
  • Multi-Gate MOSFETs

Fingerprint Dive into the research topics of 'Compact capacitance modeling of a 3-terminal FET at zero drain-source voltage'. Together they form a unique fingerprint.

  • Cite this

    Iñiguez, B., & Moldovan, O. (2010). Compact capacitance modeling of a 3-terminal FET at zero drain-source voltage. Solid-State Electronics, 54(5), 520-523. https://doi.org/10.1016/j.sse.2009.12.039