Combined nanoscale and device-level degradation analysis of SiO2 layers of MOS nonvolatile memory devices

M. Lanza, M. Porti, M. Nafría, X. Aymerich, A. Sebastiani, G. Ghidini, A. Vedda, M. Fasoli

Research output: Contribution to journalArticleResearchpeer-review

11 Citations (Scopus)
Original languageEnglish
Pages (from-to)529-536
JournalIEEE Transactions on Device and Materials Reliability
Issue number4
Publication statusPublished - 1 Jan 2009

Cite this