Combined nanoscale and device-level degradation analysis of SiO2 layers of MOS nonvolatile memory devices

M. Lanza, M. Porti, M. Nafría, X. Aymerich, A. Sebastiani, G. Ghidini, A. Vedda, M. Fasoli

Research output: Contribution to journal › Article › Research › peer-review

11 Citations (Scopus)

Original language	English
Pages (from-to)	529-536
Journal	IEEE Transactions on Device and Materials Reliability
Volume	9
Issue number	4
DOIs	https://doi.org/10.1109/TDMR.2009.2027228
Publication status	Published - 1 Jan 2009

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title = "Combined nanoscale and device-level degradation analysis of SiO2 layers of MOS nonvolatile memory devices",

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T1 - Combined nanoscale and device-level degradation analysis of SiO2 layers of MOS nonvolatile memory devices

AU - Lanza, M.

AU - Porti, M.

AU - Nafría, M.

AU - Aymerich, X.

AU - Sebastiani, A.

AU - Ghidini, G.

AU - Vedda, A.

AU - Fasoli, M.

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DO - 10.1109/TDMR.2009.2027228

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VL - 9

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EP - 536

JO - IEEE Transactions on Device and Materials Reliability

JF - IEEE Transactions on Device and Materials Reliability

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