Abstract
Threshold voltage (V T) and mobility (μ) shifts due to process related variability and Channel-Hot Carrier (CHC) degradation are experimentally characterized in strained and unstrained pMOSFETs. A simulation technique to include the time-dependent variabilities of V T and μ in circuit simulators is presented and used to evaluate their effects on CMOS inverters performance. © 2012 Elsevier Ltd. All rights reserved.
Original language | English |
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Pages (from-to) | 1924-1927 |
Journal | Microelectronics Reliability |
Volume | 52 |
DOIs | |
Publication status | Published - 1 Sep 2012 |