# Channel hot-carrier degradation in short-channel transistors with high-k/metal gate stacks

Esteve Amat, Thomas Kauerauf, Robin Degraeve, An De Keersgieter, Rosana Rodríguez, Montserrat Nafría, Xavier Aymerich, Guido Groeseneken

Research output: Contribution to journalArticleResearchpeer-review

42 Citations (Scopus)

## Abstract

Channel hot-carrier (CHC) degradation in nMOS transistors is studied for different $\hbox{SiO}-{2}/\hbox{HfSiON}$ dielectric stacks and compared to $\hbox{SiO}-{2}$. We show that, independent of the gate dielectric, in short-channel transistors, the substrate current peak (used as a measure for the highest degradation) is at $V-{G} = V-{D}$, whereas for longer channels, the maximum peak is near $V-{G} = V-{D}/\hbox{2}$. We demonstrate that this shift in the most damaging CHC condition is not caused by the presence of the high- $k$ layer but by short-channel effects. Furthermore, the CHC lifetime of short-channel transistors was evaluated at the most damaging condition $V-{G} = V-{D}$ , revealing sufficient reliability and even larger operating voltages for the high- $k$ stacks than for the $\hbox{SiO}-{2}$ reference. © 2006 IEEE.
Original language English 5062293 425-430 IEEE Transactions on Device and Materials Reliability 9 https://doi.org/10.1109/TDMR.2009.2024129 Published - 1 Sep 2009

• High-k
• Hot carriers