TY - BOOK
T1 - Carbon nanotube field-effect transistor performance in the scope of the 2026 ITRS requirements
AU - Pacheco-Sanchez, Anibal
AU - Loroch, Dominik
AU - Mothes, Sven
AU - Schroter, Michael
AU - Claus, Martin
PY - 2016/9/6
Y1 - 2016/9/6
N2 - Top gate, global back gate and buried gate CNTFET structures with a channel length of 5.9 nm are studied in the scope of the 2026 ITRS requirements. The studies are performed using a numerical device simulator. Figures of merit and performance parameters such as the switching speed, the switching energy, Ion/Ioff-ratio, among others, are obtained for each structure and compared with the 2026 ITRS requirements for different application scenarios. Most of the requirements are met with the buried gate CNTFET. The requirement for the Ion/Ioff-ratio is met at the cost of other performance parameters
AB - Top gate, global back gate and buried gate CNTFET structures with a channel length of 5.9 nm are studied in the scope of the 2026 ITRS requirements. The studies are performed using a numerical device simulator. Figures of merit and performance parameters such as the switching speed, the switching energy, Ion/Ioff-ratio, among others, are obtained for each structure and compared with the 2026 ITRS requirements for different application scenarios. Most of the requirements are met with the buried gate CNTFET. The requirement for the Ion/Ioff-ratio is met at the cost of other performance parameters
U2 - 10.1109/sispad.2016.7605201
DO - 10.1109/sispad.2016.7605201
M3 - Proceeding
T3 - 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
BT - Carbon nanotube field-effect transistor performance in the scope of the 2026 ITRS requirements
ER -