TY - JOUR
T1 - Bitplane image coding with parallel coefficient processing
AU - Aulí-Llinàs, Francesc
AU - Enfedaque, Pablo
AU - Moure, Juan C.
AU - Sanchez, Victor
N1 - Funding Information:
This work was supported in part by the EU Marie Curie Career Integration Grants Programme under Grant PIMCO, in part by the Spanish Government within the Ministerio de Econom?a y Competitividad and the Fonds Europ?en de D?veloppement ?conomique et R?gional under under Grant RYC-2010-05671, Grant TIN2015-71126-R, Grant TIN2012-38102-C03-03, Grant TIN2014-53234-C2-1-R, and Grant TIN2011-28689-C02-1, in part by the U.K. Engineering and Physical Sciences Research Council, in part by the Universitat Autonoma de Barcelona under Grant UAB-472-02-2/2012, and in part by the Catalan Government under Grant 2014SGR-691. The associate editor coordinating the review of this manuscript and approving it for publication was Dr. Ysui-Lam Chan.
Publisher Copyright:
© 2015 IEEE.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.
PY - 2016/1
Y1 - 2016/1
N2 - Image coding systems have been traditionally tailored for multiple instruction, multiple data (MIMD) computing. In general, they partition the (transformed) image in codeblocks that can be coded in the cores of MIMD-based processors. Each core executes a sequential flow of instructions to process the coefficients in the codeblock, independently and asynchronously from the others cores. Bitplane coding is a common strategy to code such data. Most of its mechanisms require sequential processing of the coefficients. The last years have seen the upraising of processing accelerators with enhanced computational performance and power efficiency whose architecture is mainly based on the single instruction, multiple data (SIMD) principle. SIMD computing refers to the execution of the same instruction to multiple data in a lockstep synchronous way. Unfortunately, current bitplane coding strategies cannot fully profit from such processors due to inherently sequential coding task. This paper presents bitplane image coding with parallel coefficient (BPC-PaCo) processing, a coding method that can process many coefficients within a codeblock in parallel and synchronously. To this end, the scanning order, the context formation, the probability model, and the arithmetic coder of the coding engine have been re-formulated. The experimental results suggest that the penalization in coding performance of BPC-PaCo with respect to the traditional strategies is almost negligible.
AB - Image coding systems have been traditionally tailored for multiple instruction, multiple data (MIMD) computing. In general, they partition the (transformed) image in codeblocks that can be coded in the cores of MIMD-based processors. Each core executes a sequential flow of instructions to process the coefficients in the codeblock, independently and asynchronously from the others cores. Bitplane coding is a common strategy to code such data. Most of its mechanisms require sequential processing of the coefficients. The last years have seen the upraising of processing accelerators with enhanced computational performance and power efficiency whose architecture is mainly based on the single instruction, multiple data (SIMD) principle. SIMD computing refers to the execution of the same instruction to multiple data in a lockstep synchronous way. Unfortunately, current bitplane coding strategies cannot fully profit from such processors due to inherently sequential coding task. This paper presents bitplane image coding with parallel coefficient (BPC-PaCo) processing, a coding method that can process many coefficients within a codeblock in parallel and synchronously. To this end, the scanning order, the context formation, the probability model, and the arithmetic coder of the coding engine have been re-formulated. The experimental results suggest that the penalization in coding performance of BPC-PaCo with respect to the traditional strategies is almost negligible.
KW - Bitplane image coding
KW - JPEG2000
KW - Single instruction multiple data (SIMD)
UR - http://www.scopus.com/inward/record.url?scp=85009260487&partnerID=8YFLogxK
U2 - 10.1109/TIP.2015.2484069
DO - 10.1109/TIP.2015.2484069
M3 - Artículo
AN - SCOPUS:85009260487
VL - 25
SP - 209
EP - 219
IS - 1
M1 - 7283609
ER -