@book{71c9e389324b4f218a50d6dc4480ba20,
title = "Analysis of traps-related effects hindering GFETs performance",
abstract = "The effect of traps on DC and high-frequency behavior of a short channel single-layer graphene field-effect transistor (GFET) is discussed thoroughly in the present work. Trap-induced hysteresis is evident when a standard staircase measurement technique is applied while it is diminished when an opposing-pulse method is used. In both cases, forward and backward gate voltage (VGS) sweeps are utilized. A recently proposed analytical compact model accounting for traps activated both by vertical electric field and high-lateral electric field enabled by hot carriers, is accurately validated with both trap-affected and trap-reduced data. Important high-frequency figures of merit (FoM) such as cut-off and maximum oscillation frequencies as well as the intrinsic gain of the GFET under test, are also derived from the model, and exhibit a strong trap dependence through the DC operating point of the device. These FoM not only demonstrate VGS shifts, but also, they exhibit magnitude alterations due to traps impact even when the Dirac voltage of the GFET under test coincides in both forward and backward staircase measurement schemes.",
keywords = "analytical model, channel potential, GFET, high-frequency performance, hysteresis, opposing-pulse, traps",
author = "Anibal Pacheco-Sanchez and Nikolaos Mavredakis and Feijoo, \{Pedro C.\} and David Jimenez",
note = "Funding Information: ACKNOWLEDGMENT We acknowledge Prof. Henri Happy, Associate Prof. Emiliano Pallecchi and Dr. Wei Wei from Carbon group (IEMN institute, University of Lille, France) for fabricating the GFET under test. This work has received funding from the European Union{\textquoteright}s Horizon 2020 Research and Innovation Programme under Grant Agreement No. GrapheneCore3 881603. It has also received partial funding from the Spanish Government under the project RTI2018-097876-B-C21 (MCIU/AEI/FEDER, UE); and partial funding from the ERDF allocated to the Programa Operatiu FEDER de Catalunya 2014-2020, with the support of the Secretaria d{\textquoteright}Universitats i Recerca of the Departament d{\textquoteright}Empresa i Coneixement of the Generalitat de Catalunya for emerging technology clusters to carry out valorization and transfer of research results. Reference of the GraphCAT project: 001-P-001702. Publisher Copyright: {\textcopyright} 2021 IEEE.",
year = "2021",
month = jun,
day = "9",
doi = "10.1109/CDE52135.2021.9455722",
language = "English",
series = "Proceedings of the 2021 13th Spanish Conference on Electron Devices, CDE 2021",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",
}