Analysis of the degradation of HfO<inf>2</inf>/SiO<inf>2</inf> gate stacks using nanoscale and device level techniques

L. Aguilera; E. Amat; R. Rodríguez; M. Porti; M. Nafría; X. Aymerich

doi:https://doi.org/10.1016/j.mee.2007.01.238

Analysis of the degradation of HfO<inf>2</inf>/SiO<inf>2</inf> gate stacks using nanoscale and device level techniques

L. Aguilera, E. Amat, R. Rodríguez, M. Porti, M. Nafría, X. Aymerich

Department of Electronic Engineering

Research output: Contribution to journal › Article › Research › peer-review

2 Citations (Scopus)

Abstract

In this work, standard device level and nanoscale electrical tests have been carried out to evaluate the influence of the high-k and interfacial SiO2 layers on the degradation of HfO2/SiO2 gate stacks. At device level, the effect of static and dynamic electrical stresses has been investigated to evaluate the influence of the voltage polarity in the degradation of the gate stack. At nanoscale level, a Conductive Atomic Force Microscope (C-AFM) has allowed to separately investigate the effect of the electrical stress on the SiO2 and HfO2 layers. © 2007 Elsevier B.V. All rights reserved.

Original language	English
Pages (from-to)	1618-1621
Journal	Microelectronic Engineering
Volume	84
DOIs	https://doi.org/10.1016/j.mee.2007.01.238
Publication status	Published - 1 May 2007

Keywords

CMOS
Dielectric breakdown
High-k
Oxide reliability

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title = "Analysis of the degradation of HfO2/SiO2 gate stacks using nanoscale and device level techniques",

abstract = "In this work, standard device level and nanoscale electrical tests have been carried out to evaluate the influence of the high-k and interfacial SiO2 layers on the degradation of HfO2/SiO2 gate stacks. At device level, the effect of static and dynamic electrical stresses has been investigated to evaluate the influence of the voltage polarity in the degradation of the gate stack. At nanoscale level, a Conductive Atomic Force Microscope (C-AFM) has allowed to separately investigate the effect of the electrical stress on the SiO2 and HfO2 layers. {\textcopyright} 2007 Elsevier B.V. All rights reserved.",

keywords = "CMOS, Dielectric breakdown, High-k, Oxide reliability",

author = "L. Aguilera and E. Amat and R. Rodr{\'i}guez and M. Porti and M. Nafr{\'i}a and X. Aymerich",

year = "2007",

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doi = "https://doi.org/10.1016/j.mee.2007.01.238",

language = "English",

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T1 - Analysis of the degradation of HfO2/SiO2 gate stacks using nanoscale and device level techniques

AU - Aguilera, L.

AU - Amat, E.

AU - Rodríguez, R.

AU - Porti, M.

AU - Nafría, M.

AU - Aymerich, X.

PY - 2007/5/1

Y1 - 2007/5/1

N2 - In this work, standard device level and nanoscale electrical tests have been carried out to evaluate the influence of the high-k and interfacial SiO2 layers on the degradation of HfO2/SiO2 gate stacks. At device level, the effect of static and dynamic electrical stresses has been investigated to evaluate the influence of the voltage polarity in the degradation of the gate stack. At nanoscale level, a Conductive Atomic Force Microscope (C-AFM) has allowed to separately investigate the effect of the electrical stress on the SiO2 and HfO2 layers. © 2007 Elsevier B.V. All rights reserved.

AB - In this work, standard device level and nanoscale electrical tests have been carried out to evaluate the influence of the high-k and interfacial SiO2 layers on the degradation of HfO2/SiO2 gate stacks. At device level, the effect of static and dynamic electrical stresses has been investigated to evaluate the influence of the voltage polarity in the degradation of the gate stack. At nanoscale level, a Conductive Atomic Force Microscope (C-AFM) has allowed to separately investigate the effect of the electrical stress on the SiO2 and HfO2 layers. © 2007 Elsevier B.V. All rights reserved.

KW - CMOS

KW - Dielectric breakdown

KW - High-k

KW - Oxide reliability

U2 - https://doi.org/10.1016/j.mee.2007.01.238

DO - https://doi.org/10.1016/j.mee.2007.01.238

M3 - Article

VL - 84

SP - 1618

EP - 1621

ER -