Analysis of the degradation of HfO<inf>2</inf>/SiO<inf>2</inf> gate stacks using nanoscale and device level techniques

L. Aguilera, E. Amat, R. Rodríguez, M. Porti, M. Nafría, X. Aymerich

Research output: Contribution to journalArticleResearchpeer-review

2 Citations (Scopus)

Abstract

In this work, standard device level and nanoscale electrical tests have been carried out to evaluate the influence of the high-k and interfacial SiO2 layers on the degradation of HfO2/SiO2 gate stacks. At device level, the effect of static and dynamic electrical stresses has been investigated to evaluate the influence of the voltage polarity in the degradation of the gate stack. At nanoscale level, a Conductive Atomic Force Microscope (C-AFM) has allowed to separately investigate the effect of the electrical stress on the SiO2 and HfO2 layers. © 2007 Elsevier B.V. All rights reserved.
Original languageEnglish
Pages (from-to)1618-1621
JournalMicroelectronic Engineering
Volume84
DOIs
Publication statusPublished - 1 May 2007

Keywords

  • CMOS
  • Dielectric breakdown
  • High-k
  • Oxide reliability

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