Accelerating Techniques for Particle Filter Implementations on FPGA

Particle filters (PFs) are Bayesian-based estimation algorithms with attractive theoretical properties for addressing a wide range of complex applications that are nonlinear and non-Gaussian. However, they are associated with a huge computational demand that limited their application in most real-time systems. To address this drawback in PFs, this chapter presents PF acceleration techniques based on a hardware/software codesign approach for the grid-based fast simultaneous localization and mapping (SLAM) application. With initial identification of the computationally intensive steps of the algorithm, techniques are proposed to accelerate the computational bottleneck steps. Based on the proposed PF acceleration techniques, hardware blocks are designed to speed up the computational time and interface in a central MicroBlaze soft processing core platform. The proposed hardware/software implementation resulted in an improvement in the overall execution time of the algorithm.