Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures

Miquel Angel Senar Rosell; Shaolong Chen

doi:10.1016/j.procs.2016.05.544

Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures

Miquel Angel Senar Rosell, Shaolong Chen

Department of Computer Architecture and Operating Systems

Universitat Autònoma de Barcelona (UAB)

Research output: Chapter in Book › Chapter › Research › peer-review

Original language	English
Title of host publication	Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016)
Subtitle of host publication	Proc. International Conference on Computational Science 2016, (ICCS 2016)
Place of Publication	(NL)
Publisher	Elsevier
Pages	2438-2442
Number of pages	4
Volume	80
Edition	1
DOIs	https://doi.org/10.1016/j.procs.2016.05.544
Publication status	Published - 1 Jan 2016

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10.1016/j.procs.2016.05.544

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Senar Rosell, M. A., & Chen, S. (2016). Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. In Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016): Proc. International Conference on Computational Science 2016, (ICCS 2016) (1 ed., Vol. 80, pp. 2438-2442). Elsevier. https://doi.org/10.1016/j.procs.2016.05.544

Senar Rosell, Miquel Angel ; Chen, Shaolong. / Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016): Proc. International Conference on Computational Science 2016, (ICCS 2016). Vol. 80 1. ed. (NL) : Elsevier, 2016. pp. 2438-2442

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Senar Rosell, MA & Chen, S 2016, Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. in Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016): Proc. International Conference on Computational Science 2016, (ICCS 2016). 1 edn, vol. 80, Elsevier, (NL), pp. 2438-2442. https://doi.org/10.1016/j.procs.2016.05.544

Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. / Senar Rosell, Miquel Angel; Chen, Shaolong.
Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016): Proc. International Conference on Computational Science 2016, (ICCS 2016). Vol. 80 1. ed. (NL): Elsevier, 2016. p. 2438-2442.

Research output: Chapter in Book › Chapter › Research › peer-review

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Senar Rosell MA, Chen S. Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures. In Procedia Computer Science (Proc, International Conference on Computational Science, ICCS 2016): Proc. International Conference on Computational Science 2016, (ICCS 2016). 1 ed. Vol. 80. (NL): Elsevier. 2016. p. 2438-2442 doi: 10.1016/j.procs.2016.05.544

Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures

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