AC-ICAP: A flexible high speed ICAP controller

Luis Andres Cardona*, Carles Ferrer

*Corresponding author for this work

Research output: Contribution to journalArticleResearchpeer-review

10 Citations (Scopus)

Abstract

The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAS). We developed a new high speed ICAP controller, named AC-ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC-ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAS. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 s which implies a speed-up of more than 380x compared to the Xilinx XPS-HWICAP controller.

Original languageAmerican English
Article number314358
JournalInternational Journal of Reconfigurable Computing
Volume2015
DOIs
Publication statusPublished - 2015

Fingerprint Dive into the research topics of 'AC-ICAP: A flexible high speed ICAP controller'. Together they form a unique fingerprint.

Cite this