A versatile CMOS transistor array IC for the statistical characterization of time-zero variability, RTN, BTI, and HCI

Javier Diaz-Fortuny, Javier Martin-Martinez, Rosana Rodriguez, Rafael Castro-Lopez, Elisenda Roca, Xavier Aragones, Enrique Barajas, Diego Mateo, Francisco V. Fernandez, Montserrat Nafria

Research output: Contribution to journalArticleResearch

15 Citations (Scopus)

Abstract

Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 mu m(2).

Original languageEnglish
Article number8563053
Pages (from-to)476-488
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number2
Publication statusPublished - 1 Feb 2019

Keywords

  • Aging
  • CMOS
  • bias temperature instability (BTI)
  • degradation
  • hot carrier injection (HCI)
  • negative BTI (NBTI)
  • positive BTI (PBTI)
  • random telegraph noise (RTN)
  • reliability
  • statistical characterization
  • variability

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