TY - JOUR
T1 - A versatile CMOS transistor array IC for the statistical characterization of time-zero variability, RTN, BTI, and HCI
AU - Diaz-Fortuny, Javier
AU - Martin-Martinez, Javier
AU - Rodriguez, Rosana
AU - Castro-Lopez, Rafael
AU - Roca, Elisenda
AU - Aragones, Xavier
AU - Barajas, Enrique
AU - Mateo, Diego
AU - Fernandez, Francisco V.
AU - Nafria, Montserrat
PY - 2019/2/1
Y1 - 2019/2/1
N2 - Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 mu m(2).
AB - Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 mu m(2).
KW - Aging
KW - CMOS
KW - bias temperature instability (BTI)
KW - degradation
KW - hot carrier injection (HCI)
KW - negative BTI (NBTI)
KW - positive BTI (PBTI)
KW - random telegraph noise (RTN)
KW - reliability
KW - statistical characterization
KW - variability
UR - http://www.mendeley.com/research/versatile-cmos-transistor-array-ic-statistical-characterization-timezero-variability-rtn-bti-hci
M3 - Article
VL - 54
SP - 476
EP - 488
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 2
M1 - 8563053
ER -