A validation and performance evaluation tool for ProtoNoC

David Castells-Rufas*, Jaume Joven, Jordi Carrabina

*Corresponding author for this work

Research output: Chapter in BookChapterResearchpeer-review

8 Citations (Scopus)


Simulating a NoC at the RTL level can be extremely complex, the simulation of a relatively small NoC, such as a 4×4 mesh, can involve observing thousands of wires on a standard HDL simulator. The facilities of JHDL to extend the simulator environment together with the possibility to fully analyze the runtime object model of the circuit offers a great opportunity to develop modules that address complex features like high level validation and performance evaluation. We present a developed tool that allows defining a NoC architecture models with some flexibility. Traffic generation processes described with high level language can be added to the model. Simulation can be used to validate the system operation on realistic conditions and get accurate values of expected performance.

Original languageEnglish
Title of host publication2006 International Symposium on System-on-Chip, SOC
Publication statusPublished - 2006

Publication series

Name2006 International Symposium on System-on-Chip, SOC


Dive into the research topics of 'A validation and performance evaluation tool for ProtoNoC'. Together they form a unique fingerprint.

Cite this