TY - BOOK
T1 - A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging
AU - Diaz-Fortuny, J.
AU - Martin-Martinez, J.
AU - Rodriguez, R.
AU - Nafria, M.
AU - Castro-Lopez, R.
AU - Roca, E.
AU - Fernandez, F.V.
AU - Barajas, E.
AU - Aragones, X.
AU - Mateo, D.
PY - 2017
Y1 - 2017
N2 - In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.
AB - In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.
UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-85027529924&partnerID=MN8TOARS
U2 - 10.1109/SMACD.2017.7981600
DO - 10.1109/SMACD.2017.7981600
M3 - Proceeding
SN - 978-1-5090-5053-6
BT - A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging
ER -