A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs

P. Martin-Lloret; A. Toro-Frias; J. Martin-Martinez; R. Castro-Lopez; E. Roca; R. Rodriguez; M. Nafria; F. V. Fernandez; null IEEE

A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs

P. Martin-Lloret, A. Toro-Frias, J. Martin-Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria, F. V. Fernandez, IEEE

Department of Electronic Engineering

Research output: Chapter in Book › Chapter › Research › peer-review

3 Citations (Web of Science)

Original language	Undefined/Unknown
Title of host publication	2017 Ieee International Symposium on Circuits and Systems (Iscas)
Publication status	Published - 2017

Cite this

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title = "A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs",

author = "P. Martin-Lloret and A. Toro-Frias and J. Martin-Martinez and R. Castro-Lopez and E. Roca and R. Rodriguez and M. Nafria and Fernandez, {F. V.} and IEEE",

year = "2017",

language = "Indefinido/desconocido",

booktitle = "2017 Ieee International Symposium on Circuits and Systems (Iscas)",

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TY - CHAP

T1 - A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs

AU - Martin-Lloret, P.

AU - Toro-Frias, A.

AU - Martin-Martinez, J.

AU - Castro-Lopez, R.

AU - Roca, E.

AU - Rodriguez, R.

AU - Nafria, M.

AU - Fernandez, F. V.

AU - IEEE, null

PY - 2017

Y1 - 2017

UR - http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000424890101242&KeyUID=WOS:000424890101242

M3 - Capítulo

BT - 2017 Ieee International Symposium on Circuits and Systems (Iscas)

ER -

A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs

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Cite this