A model for gate-oxide breakdown in CMOS inverters

R. Rodríguez; J. H. Stathis; B. P. Linder

doi:10.1109/LED.2002.808155

A model for gate-oxide breakdown in CMOS inverters

R. Rodríguez, J. H. Stathis, B. P. Linder

Department of Electronic Engineering

Research output: Contribution to journal › Article › Research › peer-review

82 Citations (Scopus)

Abstract

The effect of oxide breakdown (BD) on the performance of CMOS Inverters has been investigated. The results show that the inverter performance can be affected by the BD in a different way depending on the stress polarity applied to the inverter input. In all the cases, the oxide BD conduction has been modeled as gate-to-diffusion leakage with a power-law formula of the type I = KVp, which was previously found to describe the BD in capacitor structures. This implies that the BD physics at oxide level is the same as that at circuit level.

Original language	English
Pages (from-to)	114-116
Journal	IEEE Electron Device Letters
Volume	24
Issue number	2
DOIs	https://doi.org/10.1109/LED.2002.808155
Publication status	Published - 1 Feb 2003

Keywords

CMOS
Dielectric breakdown
Hard breakdown (HBD)
Leakage currents
Oxide breakdown
Oxide reliability

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KW - Dielectric breakdown

KW - Hard breakdown (HBD)

KW - Leakage currents

KW - Oxide breakdown

KW - Oxide reliability

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